1. Field of the Invention
The invention relates to techniques for refreshing dynamic memory, and more particularly, techniques for managing such refreshes in order to minimize the impact on throughput.
2. Description of Related Art
Main memory in a computer system is typically, today, made up of dynamic random access memory (DRAM) chips organized into one or more banks. DRAM is available in several different variations, including page mode DRAMs, extended-data-out (EDO) DRAMs, burst-extended-data-out (BEDO) DRAMS, synchronous DRAMs (SDRAM), and so on. DRAM differs from static random access memory (SRAM) in that in DRAM, data is stored in a cell in the form of capacitive charge. This capacitive charge leaks over time, and therefore must be periodically read and rewritten to bring the charge back to its original level. The process of periodically reading and rewriting data into the memory is known as "refresh". A memory is referred to herein as "dynamic" as long as it requires periodic refresh; it need not be a random access memory.
The refresh rate of a particular type of DRAM is specified by the manufacturer. For example, the data sheet for the Samsung KMV1004C 4 Mb EDO DRAM specifies that all cells are to be refreshed at least once every 16 mS. Samsung Electronics, "KMV1004C/CL/CLL CMOS DRAM", Data Sheet (1995), incorporated by reference herein. This DRAM is organized internally as four bit-planes of 1024 rows of 1024 cells each, and the cells are refreshed a row at a time. The same row in all four bit planes are refreshed in parallel so 4096 cells are refreshed at once. Thus, for this DRAM, 1024 refresh cycles are required every 16 milliseconds. Stated another way, this DRAM requires one refresh cycle on average every 15.625 microseconds, with no row remaining unrefreshed for longer than 16 milliseconds. As used herein, this DRAM is said to require a "nominal" refresh rate no slower than one row every 15.625 microseconds.
In a typical computer system, main memory is organized into one or more banks containing consecutive, or at least distinct, row address ranges. Within a bank, multiple DRAM chips are connected in parallel (horizontally) to achieve the desired data path width, and vertically to achieve the desired row address range for the bank. All of the DRAM chips in a given bank of memory share the same row address strobe, and a "refresh row" is defined as all of the bit cells in a bank which are refreshed in a single refresh cycle.
Each bank of DRAM in a typical system has a command input port, an address input port and a bi-directional data port. The command input port carries signals which command the memory to read data from the memory onto the data port, write data from the data port into memory, strobe in a new column address and/or row address, perform a refresh, and so on. For fast page mode DRAMs and EDO DRAMs, for example, the command port includes a row address strobe (RAS#) signal line and a column address strobe (CAS#) signal line. All banks typically share the same CAS# signal, but have separate RAS# signals. For read or write accesses to the memory, a memory controller drives a row address onto the memory address lines, and asserts the RAS# signal for the desired bank of memory. It then drives a column address onto the memory address lines, and asserts CAS#. Depending on the state of a third signal, R/W#, the memory will read or write data, from or to the cell identified by the row and column addresses most recently specified. Because the memory has a page mode, if the memory controller desires to access other cells within the same row (also called "page"), it may do so simply by negating and reasserting the CAS# signal with a new column address on the memory address lines. As long as the RAS# signal remains active, the memory controller need not repeat the row address on the memory address lines.
Different systems performs refresh operations in different ways. Some systems refresh the memory by explicitly reading and rewriting each row of the memory within the required time frame. Many DRAMs also support a "CAS#-before-RAS#" (CBR) refresh command, in which the memory itself internally maintains a refresh counter, indicating the next row address to be refreshed. Whenever the memory controller asserts RAS# while CAS# is already active, the memory will automatically refresh the row designated by its internal refresh counter, and then increment the counter. SDRAM does not have CAS# and RAS# lines, but supports other commands on its control port to perform an internal refresh cycle.
The time required to refresh a dynamic memory is an impediment to system throughput, because any time during which a refresh takes place is time during which no other device in the system can access the memory. In addition to the time occupied by the refresh operation itself, an additional penalty is incurred due to the RAS# precharge time required before the CAS#-before-RAS# command can be asserted. The RAS# precharge time, t.sub.RP, is specified by the memory manufacturer and can typically be on the order of 40-60 nanoseconds. Typically, all banks of DRAM are refreshed in parallel, so all RAS# lines must be negated before the refresh can begin. Thus, at least a 40-60 nanosecond penalty is incurred even before the refresh begins.
Yet another penalty is incurred after the refresh completes because the memory loses the row address during a refresh. That is, a "page miss" is guaranteed after a refresh. All of the RAS# lines must therefore be negated again for the required precharge time, and then the appropriate one reasserted to clock in the desired row address for further accesses. Thus another 40-60 nanosecond delay is incurred after the refresh completes. The post-refresh RAS# precharge delay might have been incurred anyway if the next access would have required a new row address, but a refresh operation guarantees this delay.
A refresh operation also can sometimes introduce arbitration delays, if more than one master is permitted to arbitrate for control of the DRAM. For example, many systems permit a CPU, a PCI-bus controller, and a video controller to all arbitrate for control of the memory. As with the RAS# precharge penalty, the arbitration penalty can be incurred not only after a refresh, but also before a refresh operation, at which time the refresh controller is also arbitrating for control of the memory. Arbitration delays can often be hidden, that is, they can often take place in the background while some other necessary operation is taking place with respect to the memory. But in some situations, the arbitration delays cannot be completely hidden.
Some systems attempt to minimize the impact on throughput by performing "burst refreshes". A burst refresh controller in such a system accumulates a predetermined number of refresh requests from a refresh timer, and then arbitrates for control of the memory only once to perform all accumulated refreshes. If a system bursts four refreshes at a time, for example, three page-miss delays before a refresh cycle and up to three page-miss delays after a refresh cycle, and up to six arbitration delays, are avoided.
Thus, a burst refresh memory controller improves system throughput by reducing the overhead associated with the refresh activity. A new problem is introduced, however, that of memory access latency. Whereas in a non-burst refresh system another device requesting access to the memory (such as the CPU) had to wait up to the total time of a refresh cycle (plus overhead) in order to gain control of the memory, the amount of time such a device must wait in a burst refresh system can be as great as the total time of the entire burst (plus overhead).
Accordingly, there is a need for a way to increase the flexibility with which a refresh controller can perform burst refreshes. Advantageously, the refresh controller should be capable of greater flexibility in choosing when to initiate a burst refresh, as well as in choosing the length of each burst, in order to better maximize the number of refresh cycles that occur while the memory would otherwise be idle.